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S. Lee, S. Hara, T. Yoshida, S. Amakawa, R. Dong, A. Kasamatsu, J. Sato, and M. Fujishima, "An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver," IEEE Journal of Solid-State Circuits, vol. 54, iss. 12, pp. 3577–3588, Dec. 2019.
DOI: 10.1109/JSSC.2019.2944855
ID no. (ISBN etc.): 1558-173X
BibTeX citation key: Lee2019.1
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Categories: General
Keywords: CMOS integrated circuits;field effect MIMIC;frequency multipliers;millimetre wave mixers;power combiners;single-chip CMOS transceiver;IEEE Std 802.15.3d;TRX chip;mixer-last architecture;ring circuit;double-rat-race;fundamental-mixer-first direct-conversion architecture;LO multiplier chain;low-characteristic-impedance transmission lines;CMOS process;wireless data rate;transmitter mode;receiver mode;NMOSFET;frequency-doubler-based upconversion mixer;low-loss impedance transmission lines;16QAM;four-way power combining;power 890.0 mW;noise figure 22.9 dB;power 897.0 mW;frequency 252.0 GHz to 279.0 GHz;bit rate 80 Gbit/s;frequency 300 GHz;size 40 nm;distance 3.0 cm;Mixers;Wireless communication;IEEE 802.15 Standard;Layout;Quadrature amplitude modulation;Frequency modulation;Beyond 5G;near-fₘₐₓ circuits;terahertz wireless communication
Creators: Amakawa, Dong, Fujishima, Hara, Kasamatsu, Lee, Sato, Yoshida
Collection: IEEE Journal of Solid-State Circuits
Keywords: CMOS integrated circuits;field effect MIMIC;frequency multipliers;millimetre wave mixers;power combiners;single-chip CMOS transceiver;IEEE Std 802.15.3d;TRX chip;mixer-last architecture;ring circuit;double-rat-race;fundamental-mixer-first direct-conversion architecture;LO multiplier chain;low-characteristic-impedance transmission lines;CMOS process;wireless data rate;transmitter mode;receiver mode;NMOSFET;frequency-doubler-based upconversion mixer;low-loss impedance transmission lines;16QAM;four-way power combining;power 890.0 mW;noise figure 22.9 dB;power 897.0 mW;frequency 252.0 GHz to 279.0 GHz;bit rate 80 Gbit/s;frequency 300 GHz;size 40 nm;distance 3.0 cm;Mixers;Wireless communication;IEEE 802.15 Standard;Layout;Quadrature amplitude modulation;Frequency modulation;Beyond 5G;near-fₘₐₓ circuits;terahertz wireless communication
Creators: Amakawa, Dong, Fujishima, Hara, Kasamatsu, Lee, Sato, Yoshida
Collection: IEEE Journal of Solid-State Circuits
Abstract
A single-chip CMOS transceiver (TRX) capable of wireless data rates up to 80 Gb/s using part of frequencies (252-279 GHz) covered by IEEE Std 802.15.3d is presented. The TRX chip operates in either transmitter (TX) or receiver (RX) mode at frequencies comparable to fmax of the NMOSFET. The TX part adopts mixer-last architecture with four-way power combining using a ring circuit called a double-rat-race. The RX part adopts fundamental-mixer-first direct-conversion architecture. In the RX mode, the TX serves as an LO multiplier chain, which conventionally accounted for a significant part of the RX die area. The double-rat-race, having an improved design than the original one, integrates the TX and RX and also rejects unwanted harmonics generated by the frequency-doubler-based upconversion mixer. Low-loss, low-characteristic-impedance transmission lines are used extensively to combat losses. The TRX was fabricated using a 40-nm CMOS process. The saturated output power of the TX is -1.6 dBm at 265.68 GHz. The mean single-sideband noise figure (SSB NF) of the RX is 22.9 dB. The TX mode and the RX mode consume dc power of 890 and 897 mW, respectively. A wireless data rate of 80 Gb/s between a pair of TRX chips is demonstrated with 16QAM over a distance of 3 cm.