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Keyword:  CMOS integrated circuits;field effect MIMIC;frequency multipliers;millimetre wave mixers;power combiners;single-chip CMOS transceiver;IEEE Std 802.15.3d;TRX chip;mixer-last architecture;ring circuit;double-rat-race;fundamental-mixer-first direct-conversion architecture;LO multiplier chain;low-characteristic-impedance transmission lines;CMOS process;wireless data rate;transmitter mode;receiver mode;NMOSFET;frequency-doubler-based upconversion mixer;low-loss impedance transmission lines;16QAM;four-way power combining;power 890.0 mW;noise figure 22.9 dB;power 897.0 mW;frequency 252.0 GHz to 279.0 GHz;bit rate 80 Gbit/s;frequency 300 GHz;size 40 nm;distance 3.0 cm;Mixers;Wireless communication;IEEE 802.15 Standard;Layout;Quadrature amplitude modulation;Frequency modulation;Beyond 5G;near-fₘₐₓ circuits;terahertz wireless communication
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S. Lee, S. Hara, T. Yoshida, S. Amakawa, R. Dong, A. Kasamatsu, J. Sato, and M. Fujishima, "An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver," IEEE Journal of Solid-State Circuits, vol. 54, iss. 12, pp. 3577–3588, Dec. 2019.  
2020-12-23 11:08:19
WIKINDX 6.4.0 | Total resources: 1 | Username: -- | Bibliography: WIKINDX Master Bibliography | Style: Institute of Electrical and Electronics Engineers (IEEE) | Database queries: 20 | DB execution: 0.01089 secs | Script execution: 0.10103 secs